1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming the semiconductor structures, and more particularly to stacked structures and methods of forming the stacked structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chipsets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. In order to achieve these targets, stacking technology has been applied to assemble two or more dies together, thereby providing multi-function chips and reducing chip dimensions.
FIG. 1A shows top views of two wafers. Different dies 103 and 113 are formed over wafers 100 and 110, respectively. Bonding pads (not shown) are formed in the dies 103 and 113. The wafers 100 and 110 are can be assembled into stacked structures by bonding the pads formed thereon. In each wafer, the dies 103 and 113 are separated by scribe lines 105 and 115, respectively. After the formation of the dies 103 and 113, the wafer 110 is bonded over the wafer 100 by a bonding step before singulation of the dies along the scribe lines.
FIG. 1B shows a cross-sectional view of the bonded wafers taken along a section line (not shown) which passes through one of the scribe lines 105, 115 shown in FIG. 1A. As shown in FIG. 1B, the wafers 100 and 110 are bonded at the bonding pads 107 and 117 formed over the wafers 100 and 110, respectively. After the formation of the stacked wafers 100 and 110, the backsides of the wafers 100 and 110 are subjected to grinding steps for reducing thicknesses of the wafers 100 and 110. The ground wafers are then subjected to a sawing (singulation) step for obtaining individual stacked dies.
As shown in FIG. 1B, no isolation material is filled between the bonded wafers 100 and 110. When the bonded wafers 100 and 110 are subjected to the grinding steps, such as chemical mechanical planarization (CMP) processing steps, chemicals or particles 109 may flow into the gap between the wafers 100 and 110, to the pads 107 and 117 or die areas (not shown) along scribe lines, resulting in shorts between devices or circuits (not shown) formed in the die areas. In order to solve the problem, some protective structures have been proposed.
FIG. 1C shows top views of two wafers upon which different dies are formed. FIG. 1D shows enlarged dies 123 and 133 shown in FIG. 1C.
Referring to FIG. 1C, dies 123 and 133 are formed over the wafers 120 and 130, respectively. In addition, protective structures 125, 127, 135 and 137 are also formed over the wafers 120 and 130, respectively. The protective structures 125 and 135 are formed, surrounding the dies 123 and 133, respectively. The protective structures 127 and 137 having patterns different from the dies 123 and 133 are formed over the peripheral areas of the wafers 120 and 130, where no integrated circuit, i.e., functional circuit, is formed.
As shown in FIG. 1D, each of the protective structures 125 and 135 comprises a plurality of rings. When the wafer 130 is bonded over the wafer 120, the rings of the protective structures 125 are also aligned and bonded to the corresponding rings of the protective structures 135, and the protective structures 127 are aligned and bonded to the corresponding protective structures 137. By the bonding step, the peripheral areas of the bonded wafers 120 and 130 are divided into many isolated areas separated by the protective structures 127 and 137, each of which is isolated or sealed by the protective structures 127 and 137. Accordingly, when the bonded wafers 120 and 130 are subjected to a CMP step, the protective structures 127 and 137 block chemicals at the circumference of the bonded wafers 120 and 130 and prevent penetration of chemicals to the dies 123 and 133 through the scribe lines. In addition, the bonded protective structures 125 and 135, i.e., rings, surround and individually seal the dies 123 and 133. Therefore, even if the bonded protective structures 127 and 137 fail to properly prevent penetration of chemicals at the peripheral area of the wafers, the bonded protective structures 127 and 137 around individual dies provide another shelter for blocking chemicals.
However, the protective structures 125, 127, 135 and 137 have some shortcomings. As shown in FIG. 1C, the patterns of the protective structures 127 and 137 are different from those of the dies 123 and 133. In other words, at least one additional photo reticle should be provided for patterning the protective structures 127 and 137, and the protective structures 127 and 137 must be formed by processing steps different from those of forming the dies 123 and 135. Accordingly, manufacturing costs and cycle time are increased. In addition, the rings of the protective structures 125 and 135 must be well aligned; otherwise, the rings of the protective structures 125 and 135 cannot connect to each other, and desirably sealed spaces between the rings cannot be formed. Accordingly, misalignment of the protective structures 125 and 135 adversely affects the function of the bonded protective structures 125 and 135.
From the foregoing, stacked structures and methods of forming the stacked structures are desired.